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High Speed Physical Layer with Data Independent Single Byte Checksum

Nagaraju V, Siddanna Gowd L. C.

Abstract


Fast and reliable wireless communication is essential need of current scenario. Without the proper design of Physical layer, the speedy communication is not practically achievable. The network traffic processing often gets delayed due to the high volume and the complex nature of the network traffic. Hence the computation with high performance is required for processing the traffic. High performance in computation is not possible with a single device. Using parallel processing, the load can be divided among multiple devices. Yet another issue with the processing of traffic is protecting the data against malicious activities. In this paper high speed physical layer is achieved by a novel authentication bit generation method and parallel processing. Reconfigurable hardware is designed to achieve reliable and high speed physical layer depending upon the network conditions. Reconfigurable hardware create space for the functional modifications post-fabrication. This helps in fixing bugs and functional upgrade of the system. Also allows sharing hardware resources among different tasks which are inactive simultaneously. The size of the authentication bit is reduced in the high speed physical layer. The authentication bit is generated independent of user data, thus allows for parallelism in high speed physical layer.


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